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cy8c21634, cy8c21534 CY8C21434, cy8c 21334, cy8c21234 psoc ? mixed-signal array cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 38-12025 rev. *m revised april 18, 2008 features powerful harvard architecture processor ? m8c processor speeds to 24 mhz ? low power at high speed ? 2.4v to 5.25v operating voltage ? operating voltages down to 1.0v using on-chip switch mode pump (smp) ? industrial temperature range: -40c to +85c advanced peripherals (psoc blocks) ? 4 analog type ?e? psoc blocks provide: ? 2 comparators with dac refs ? single or dual 8-bit 28 channel adc ? 4 digital psoc blocks provide: ? 8 to 32-bit timers, counters, and pwms ? crc and prs modules ? full-duplex uart, spi ? master or slave ? connectable to all gpio pins ? complex peripherals by combining blocks flexible on-chip memory ? 8k flash program storage 50,000 erase/write cycles ? 512 bytes sram data storage ? in-system serial programming (issp ? ) ? partial flash updates ? flexible protection modes ? eeprom emulation in flash complete development tools ? free development software (psoc designer?) ? full-featured, in-circuit emulator and programmer ? full speed emulation ? complex breakpoint structure ? 128k trace memory precision, programmable clocking ? internal 2.5% 24/48 mhz oscillator ? internal oscillator for watchdog and sleep programmable pin configurations ? 25 ma drive on all gpio ? pull up, pull down, high z, strong, or open drain drive modes on all gpio ? up to 8 analog inputs on gpio ? configurable interrupt on all gpio versatile analog mux ? common internal analog bus ? simultaneous connection of io combinations ? capacitive sensing application capability additional system resources ? i 2 c? master, slave and multi-master to 400 khz ? watchdog and sleep timers ? user-configurable low voltage detection ? integrated supervisory circuit ? on-chip precision voltage reference block diagram [+] feedback
cy8c21634, cy8c21534 CY8C21434, cy8c21334, cy8c21234 document number: 38-12025 rev. *m page 2 of 43 psoc ? functional overview the psoc? family consists of many mixed-signal array with on-chip controller devices. these devices are designed to replace multiple traditional m cu-based system components with one low cost single-chip programmable component. a psoc device includes configurable blocks of analog and digital logic, and programmable interconnect. this architecture enables the user to create customized peripheral configurations, to match the requirements of each individua l application. additionally, a fast cpu, flash program memory, sram data memory, and configurable io are included in a range of convenient pinouts. the psoc architecture, shown in figure 1 , consists of four main areas: the core, the system resources, the digital system, and the analog system. configurab le global bus resources allow combining all the device res ources into a complete custom system. each cy8c21x34 psoc de vice includes four digital blocks and four analog blo cks. depending on the psoc package, up to 28 general purpose io (gpio) are also included. the gpio provide access to the global digital and analog inter- connects. the psoc core the psoc core is a powerful engine that supports a rich instruction set. it encompasses sram for data storage, an interrupt controller, sleep and watchdog timers, and imo (internal main oscillator) and ilo (internal low speed oscillator). the cpu core, called the m8c, is a powerful processor with speeds up to 24 mhz. the m8c is a four mips 8-bit harvard architecture microprocessor. system resources provide the fo llowing additional capabilities: digital clocks to increase the flexibility of the psoc mixed-signal arrays. i2c functionality to implement an i2c master and slave. an internal voltage reference, multimaster, that provides an absolute value of 1.3v to a number of psoc subsystems. a switch mode pump (smp) that generates normal operating voltages off a single battery cell. various system resets supported by the m8c. the digital system consists of an array of digital psoc blocks that may be configured into an y number of digital peripherals. the digital blocks are connected to the gpio through a series of global buses that can route any signal to any pin, freeing designs from the constraints of a fixed peripheral controller. the analog system consists of four analog psoc blocks, supporting comparators and analog-to-digital conversion up to 8 bits in precision. the digital system the digital system consists of 4 digital psoc blocks. each block is an 8-bit resource that is used alone or combined with other blocks to form 8, 16, 24, and 32 -bit peripherals, which are called user module references. digital peripheral configurations include the following. pwms (8 to 32 bit) pwms with dead band (8 to 32 bit) counters (8 to 32 bit) timers (8 to 32 bit) uart 8 bit with selectable parity spi master and slave i2c slave and multi-master cyclical redundancy checker/generator (8 to 32 bit) irda pseudo random sequence generators (8 to 32 bit) the digital blocks are connected to any gpio through a series of global buses that can route any signal to any pin. the buses also allow for signal multiplexing and for performing logic operations. this configurability frees your designs from the constraints of a fixed peripheral controller. digital blocks are provided in ro ws of four, where the number of blocks varies by psoc device fa mily. this allows the optimum choice of system resources fo r your application. family resources are shown in ta b l e 1 on page 4. figure 1. digital system block diagram digital system to system bus d i g i t a l c l o c k s f r o m c o r e digital psoc block array to analog system 8 row input configuration row output configuration 8 8 8 row 0 dbb00 dbb01 dcb02 dcb03 4 4 gie[7:0] gio[7:0] goe[7:0] goo[7:0] global digital interconnect po r t 3 po r t 2 po r t 1 po r t 0 [+] feedback
cy8c21634, cy8c21534 CY8C21434, cy8c21334, cy8c21234 document number: 38-12025 rev. *m page 3 of 43 the analog system the analog system consists of 4 configurable bl ocks that allow the creation of complex analog signal flows. analog peripherals are very flexible and may be customized to support specific application requirements. some of the common psoc analog functions for this device (most available as user modules) are: analog-to-digital converters (single or dual, with 8-bit resolution) pin-to-pin comparator single-ended comparators (up to 2) with absolute (1.3v) reference or 8-bit dac reference 1.3v reference (as a system resource) in most psoc devices, analog blo cks are provided in columns of three, which includes one ct (continuous time) and two sc (switched capacitor) blocks. the cy8c21x34 devices provide limited functionality type ?e? analog blocks. each column contains one ct type e block and one sc type e block. refer to the psoc mixed-signal array technical reference manual for detailed information on the cy8c 21x34?s type e analog blocks. figure 2. analog system block diagram the analog multiplexer system the analog mux bus can connect to every gpio pin. pins may be connected to the bus individually or in any combination. the bus also connects to the analog system for analysis with comparators and analog-to-digital converters. an additional 8:1 analog input multiplexer provides a second path to bring port 0 pins to the analog array. switch control logic enables selected pins to precharge continuously under hardware control. this enables capacitive measurement for applications su ch as touch sensing. other multiplexer applications include: track pad, finger sensing. chip-wide mux that allows analog input from any io pin. crosspoint connection between any io pin combinations. when designing capacitive sensing applications, refer to the signal-to-noise system level requirement found in application note an2403 on the cypress web site at http://www.cypress.com . additional system resources system resources, some of wh ich are listed in the previous sections, provide additional capability useful to complete systems. additional resources include a switch mode pump, low voltage detection, and power on reset. brief statements describing the merits of ea ch system resource follow. digital clock dividers provide three customizable clock frequencies for use in applications. the clocks may be routed to both the digital and analog systems. additional clocks can be generated using digital psoc blocks as clock dividers. the i2c module provides 100 and 400 khz communication over two wires. slave, master, and multi-master modes are all supported. low voltage detection (lvd) interrupts can signal the application of falling voltage levels, while the advanced por (power on reset) circuit eliminates the need for a system supervisor. an internal 1.3 voltage reference provides an absolute reference for the analog system, including adcs and dacs. an integrated switch mode pump (smp) generates normal operating voltages from a single 1.2v battery cell, providing a low cost boost converter. versatile analog mu ltiplexer system. ac o l 1 m u x ace00 ace01 array array input configuration ase10 ase11 x x x x x an a l o g mu x bus a ll io aci0[1:0] aci1[1:0] [+] feedback
cy8c21634, cy8c21534 CY8C21434, cy8c21334, cy8c21234 document number: 38-12025 rev. *m page 4 of 43 psoc device characteristics depending on your psoc device characteristics, the digital and analog systems can have 16, 8, or 4 digital blocks and 12, 6, or 4 analog blocks. table 1 lists the resources available for specific psoc device groups. the psoc de vice covered by this data sheet is highlighted in this table. getting started the quickest path to understanding the psoc silicon is by reading this data sheet and usi ng the psoc designer integrated development environment (ide). this data sheet is an overview of the psoc integrated circuit and pr esents specific pin, register, and electrical specifications. for in-depth information with detailed programming information, refer the psoc mixed-signal array technical reference manual available at http://www.cyp ress.com/psoc . for up-to-date ordering, packaging, and electrical specification information, refer the latest psoc device data sheets at http://www.cypress.com . development kits development kits are available from the following distributors: digi-key, avnet, arrow, and future. the cypress online store contains development kits, c compilers, and all accessories for psoc development. go to the cypress online store web site at http://www.cypress.com , click the online store shopping cart icon at the bottom of the web page, and click psoc (program- mable system-on-chip) to view a current list of available items. technical training modules free psoc technical training modules are available for users new to psoc. training modules cover designing, debugging, advanced analog and capsense. go to http://www.cypress. com/techtrain . consultants certified psoc consultants offer everything from technical assistance to completed psoc designs. to contact or become a psoc consultant go to http://www.cypress.com , click on design support located on the left side of the web page, and select cypros consultants. technical support psoc application engineers take pride in fast and accurate response. they can be reached with a 4-hour guaranteed response at http://www.cypress.com/support . application notes a long list of application notes c an assist you in every aspect of your design effort. to view the psoc application notes, go to the http://www.cypress.com web site and select application notes under the design resources list located in the center of the web page. application notes are sorted by date by default. development tools psoc designer is a microsoft ? windows-based, integrated development environment for the programmable system-on-chip (psoc) devices. the psoc designer ide and application runs on windows nt 4.0, windows 2000, windows millennium (me), or windows xp. (see figure 3 on page 5) psoc designer helps the customer to select an operating configuration for the psoc, writ e application code that uses the psoc, and debug the ap plication. this syst em provides design database management by project, an integrated debugger with in-circuit emulator, in-system programming support, and the cyasm macro assembler for the cpus. psoc designer also supports a high-level c language compiler developed specifically for the devices in the family. table 1. psoc device characteristics psoc part number digital io digital rows digital blocks analog inputs analog outputs analog columns analog blocks sram size flash size cy8c29x66 up to 64 4 16 12 4 4 12 2k 32k cy8c27x43 up to 44 2 8 12 4 4 12 256 bytes 16k cy8c24x94 56 1 4 48 2 2 6 1k 16k cy8c24x23a up to 24 1 4 12 2 2 6 256 bytes 4k cy8c21x34 up to 28 1 4 28 0 2 4 a a. limited analog functionality . 512 bytes 8k cy8c21x23 16 1 4 8 0 2 4 a 256 bytes 4k cy8c20x34 up to 28 0 0 28 0 0 3 b b. two analog blocks and one capsense. 512 bytes 8k [+] feedback
cy8c21634, cy8c21534 CY8C21434, cy8c21334, cy8c21234 document number: 38-12025 rev. *m page 5 of 43 figure 3. psoc designer subsystems psoc designer software subsystems device editor the device editor subsystem enables the user to select different onboard analog and digital components called user modules using the psoc blocks. examples of user modules are adcs, dacs, amplifiers, and filters. the device editor also supports easy development of multiple configurations and dynamic reconfiguration. dynamic reconfiguration allows changing configurations at run time. psoc designer sets up power on initialization tables for selected psoc block configurations and creates source code for an application framework. the framework contains software to operate the selected components and, if the project uses more than one operating configuration, contains routines to switch between different sets of psoc bl ock configurations at run time. psoc designer can print out a configuration sheet for a given project configuration for use during application programming in conjunction with the device data sheet. after the framework is generated, the user can add applic ation-specific code to flesh out the framework. it is also possible to change the selected components and regenerate the framework. design browser the design browser enables users to select and import preconfigured designs into the user?s project. users can easily browse a catalog of preconfigured designs to facilitate time-to-design. examples provided in the tools include a 300-baud modem, lin bus master and slave, fan controller, and magnetic card reader. application editor in the application editor you can edit your c language and assembly language source code. you can also assemble, compile, link, and build. assembler. the macro assembler allows the seamless merging of the assembly code with c code. the link libraries automatically use absolute addressing or are compiled in relative mode, and linked with other software modules to get absolute addressing. c language compiler. a c language compiler that supports the psoc family of devices is available. even if you have never worked in the c language before, the product quickly helps you create complete c programs for the psoc family devices. the embedded, optimizing c compiler provides all the features of c tailored to the psoc archit ecture. it comes complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. debugger the psoc designer debugger subsystem provides hardware in-circuit emulation, allowing th e designer to test the program in a physical system while providing an internal view of the psoc device. debugger commands allow the designer to read the program and read and write data memory, read and write io registers, read and write cpu r egisters, set and clear break- points, and provide program run, halt, and step control. the debugger also allows the designer to create a trace buffer of registers and memory lo cations of interest. online help system the online help system displays on line, context-sensitive help for the user. designed for procedural and quick reference, each functional subsystem has its ow n context-sensitive help. this system also provides tutorials an d links to faqs and an online support forum to aid the designer in getting started. hardware tools in-circuit emulator a low cost, high functionality ice (in-circuit emulator) is available for development support. this hardware has the capability to progra m single devices. the emulator consists of a base unit that connects to the pc by way of a usb port. the base unit is universal and operates with all psoc devices. emulation p ods for each device family are available separately. the emulation pod takes the place of the psoc device in the target board and performs full speed (24 mhz) operation. [+] feedback
cy8c21634, cy8c21534 CY8C21434, cy8c21334, cy8c21234 document number: 38-12025 rev. *m page 6 of 43 designing with user modules the development process for the psoc device differs from that of a traditional fixed function microprocessor. the configurable analog and digital hardware blocks give the psoc architecture a unique flexibility that pays divi dends in managing specification change during development and by lowering inventory costs. these configurable resources, called psoc blocks, have the ability to implement a wide variety of user-selectable functions. each block has several registers that determine its function and connectivity to other blocks, mu ltiplexers, buses and to the io pins. iterative development cycl es permit you to adapt the hardware and software. this substantially lowers the risk of having to select a different part to meet the final design requirements. to speed the development process, the psoc designer integrated development environm ent (ide) provides a library of pre-built, pre-tested hardware peripheral functions, called ?user modules.? user modules make selecting and implementing peripheral devices simple, and come in analog, digital, and mixed signal varieties. the standard user module library contains over 50 common peripherals such as adcs, dacs timers, counters, uarts, and other uncommon peripherals, such as dtmf generators and bi-quad analog filter sections. each user module establishes t he basic register settings that implement the selected function. it also provides parameters that allow you to tailor its precise configuration to your particular application. for example, a pulse width modulator user module configures one or more digital psoc blocks, one for each 8 bits of resolution. the user mo dule parameters permit you to establish the pulse width and duty cycle. user modules also provide tested software to cut your development time. the user module application programming interface (api) provides high-level functions to control and respond to hardware events at run time. the api also provides optional interrupt service routines that you can adapt as needed. the api functions are document ed in user module data sheets that are viewed directly in the psoc designer ide. these data sheets explain the internal operation of the user module and provide performance specificatio ns. each data sheet describes the use of each user module parameter and documents the setting of each register controlled by the user module. the development process starts when you open a new project and bring up the device editor, a graphical user interface (gui) for configuring the hardware. you can pick the user modules you need for your project and map them onto the psoc blocks with point-and-click simplicity. next, you build signal chains by inter- connecting user modules to each other and the io pins. at this stage, you must also configure the clock source connections and enter parameter values directly or by selecting values from drop-down menus. when you are ready to test the hardware configuration or move on to developing code for the project, perform the ?generate applicat ion? step. this causes psoc designer to generate source code that automatically configures the device to your specification and provides the high-level user module api functions. figure 4. user module and source code development flows the next step is to write your main program, and any sub-routines using psoc designer?s application editor subsystem. the application editor includes a project manager that allows you to open the project source code files (including all generated code files) from a hierarchal view. the source code editor provides syntax coloring and advanced edit features for both c and assembly language. file search capabilities include simple string searches and recursive ?grep-style? patterns. a single mouse click invokes the build manager. it employs a professional-strength ?ma kefile? system to au tomatically analyze all file dependencies and run the compiler and assembler as necessary. project-level options control optimizat ion strategies used by the compiler and linker. syntax errors are displayed in a console window. double clicking the error message takes you directly to the offending line of source code. when all is correct, the linker builds a hex file image suitable for programming. the last step in the development process takes place inside the psoc designer?s debugger subsystem. the debugger downloads the hex image to the in -circuit emulator (ice) where it runs at full speed. debugger ca pabilities rival those of systems costing many times more. in addition to traditional single-step, run-to-breakpoint and watch-variable features, the debugger provides a large trace buffer and enables you to define complex breakpoint events that include monitoring address and data bus values, memory locations, and external signals. debugger interface to ice application editor device editor project manager source code editor storage inspector user module selection placement and parameter -ization generate application build all event & breakpoint manager build manager source code generator [+] feedback
cy8c21634, cy8c21534 CY8C21434, cy8c21334, cy8c21234 document number: 38-12025 rev. *m page 7 of 43 document conventions acronyms used the following table lists the acronyms that are used in this document. units of measure a units of measure table is locat ed in the electrical specifications section. table 2 on page 7 lists all the abbreviations used to measure the psoc devices. numeric naming hexadecimal numbers are represented with all letters in uppercase with an appended lowercas e ?h? (for example, ?14h? or ?3ah?). hexadecimal numbers may also be represented by a ?0x? prefix, the c coding convention. binary numbers have an appended lowercase ?b? (for example, 01010100b? or ?01000011b?). numbers not indicat ed by an ?h?, ?b?, or 0x are decimal. table 2. acronyms used acronym description ac alternating current adc analog-to-digital converter api application programming interface cpu central processing unit ct continuous time dac digital-to-analog converter dc direct current eco external crystal oscillator eeprom electrically erasable programmable read-only memory fsr full scale range gpio general purpose io gui graphical user interface hbm human body model ice in-circuit emulator ilo internal low speed oscillator imo internal main oscillator io input/output ipor imprecise power on reset lsb least-significant bit lvd low voltage detect msb most-significant bit pc program counter pll phase-locked loop por power on reset ppor precision power on reset psoc? programmable system-on-chip? pwm pulse width modulator sc switched capacitor slimo slow imo smp switch mode pump sram static random access memory [+] feedback
cy8c21634, cy8c21534 CY8C21434, cy8c21334, cy8c21234 document number: 38-12025 rev. *m page 8 of 43 pin information the cy8c21x34 psoc device is available in a variety of packages which are listed in the following tables. every port pin (label ed with a ?p?) is capable of digital io and connection to the common anal og bus. however, vss, vdd, smp, and xres are not capable of digital io. 16-pin part pinout figure 5. cy8c21234 16-pin psoc device soic vdd p0[6], a, i, m p0[4], a, i, m p0[2], a, i, m p0[0], a, i, m p1[4], extclk, m p1[2], m p1[0], i2c sda, m 16 15 14 13 12 11 1 2 3 4 5 6 7 8 a, i, m, p0[7] a, i, m, p0[5] a, i, m, p0[3] a, i, m, p0[1] smp vss m, i2c scl, p1[1] vss 10 9 table 3. pin definition s - cy8c21234 16-pin (soic) pin no. type name description digital analog 1 io i, m p0[7] analog column mux input. 2 io i, m p0[5] analog column mux input. 3 io i, m p0[3] analog column mux input, integrating input. 4 io i, m p0[1] analog column mux input, integrating input. 5 power smp switch mode pump (smp) connection to required external components. 6 power vss ground connection. 7 io m p1[1] i2c serial clock (scl), issp-sclk*. 8 power vss ground connection. 9 io m p1[0] i2c serial data (sda), issp-sdata*. 10 io m p1[2] 11 io m p1[4] optional external clock input (extclk). 12 io i, m p0[0] analog column mux input. 13 io i, m p0[2] analog column mux input. 14 io i, m p0[4] analog column mux input. 15 io i, m p0[6] analog column mux input. 16 power vdd supply voltage. legend a = analog, i = input, o = output, and m = analog mux input. * these are the issp pins, which are not high z at por (power on reset). see the psoc mixed-signal array technical reference ma nual for details. [+] feedback
cy8c21634, cy8c21534 CY8C21434, cy8c21334, cy8c21234 document number: 38-12025 rev. *m page 9 of 43 20-pin part pinout figure 6. cy8c21334 20-pin psoc device ssop vdd p0[6], a, i, m p0[4], a, i, m p0[2], a, i, m p0[0], a, i, m xres p1[6], m p1[4], extclk, m p1[2], m p1[0], i2c sda, m 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 a, i, m, p0[7] a, i, m, p0[5] a, i, m, p0[3] a, i, m, p0[1] m, i2c scl, p1[7] sda, p1[5] m, p1 [3 ] scl, p1[1] vss vss m, i2 c m, i2 c table 4. pin definition s - cy8c21334 20-pin (ssop) pin no. type name description digital analog 1 io i, m p0[7] analog column mux input. 2 io i, m p0[5] analog column mux input. 3 io i, m p0[3] analog column mux input, integrating input. 4 io i, m p0[1] analog column mux input, integrating input. 5 power vss ground connection. 6 io m p1[7] i2c serial clock (scl). 7 io m p1[5] i2c serial data (sda). 8 io m p1[3] 9 io m p1[1] i2c serial clock (scl), issp-sclk*. 10 power vss ground connection. 11 io m p1[0] i2c serial data (sda), issp-sdata*. 12 io m p1[2] 13 io m p1[4] optional external clock input (extclk). 14 io m p1[6] 15 input xres active high external reset with internal pull down. 16 io i, m p0[0] analog column mux input. 17 io i, m p0[2] analog column mux input. 18 io i, m p0[4] analog column mux input. 19 io i, m p0[6] analog column mux input. 20 power vdd supply voltage. legend a = analog, i = input, o = output, and m = analog mux input. * these are the issp pins, which are not high z at por (power on reset). see the psoc mixed-signal array technical reference ma nual for details. [+] feedback
cy8c21634, cy8c21534 CY8C21434, cy8c21334, cy8c21234 document number: 38-12025 rev. *m page 10 of 43 28-pin part pinout figure 7. cy8c21534 28-pin psoc device a, i, m, p0[7] a, i, m, p0[5] a, i, m, p0[3] a, i, m, p0[1] m, p2 [7 ] m, p2 [5 ] m, p2 [3 ] m, p2 [1 ] vss m, i2 c scl , p1 [7 ] m, i2c sda, p1[5] m, p1 [3 ] m, i2 c scl , p1 [1 ] vss vdd p0[6], a, i, m p0[4], a, i, m p0[2], a, i, m p0[0], a, i, m p2[6], m p2[4], m p2[2], m p2[0], m xres p1[6], m p1[4], extclk, m p1[2], m p1[0], i2c sda, m ssop 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 table 5. pin definition s - cy8c21534 28-pin (ssop) pin no. type name description digital analog 1 io i, m p0[7] analog column mux input. 2 io i, m p0[5] analog column mux input and column output. 3 io i, m p0[3] analog column mux input and column output, integrating input. 4 io i, m p0[1] analog column mux input, integrating input. 5 io m p2[7] 6 io m p2[5] 7 io i, m p2[3] direct switched capacitor block input. 8 io i, m p2[1] direct switched capacitor block input. 9 power vss ground connection. 10 io m p1[7] i2c serial clock (scl). 11 io m p1[5] i2c serial data (sda). 12 io m p1[3] 13 io m p1[1] i2c serial clock (scl), issp-sclk*. 14 power vss ground connection. 15 io m p1[0] i2c serial data (sda), issp-sdata*. 16 io m p1[2] 17 io m p1[4] optional external clock input (extclk). 18 io m p1[6] 19 input xres active high external reset with internal pull down. 20 io i, m p2[0] direct switched capacitor block input. 21 io i, m p2[2] direct switched capacitor block input. 22 io m p2[4] 23 io m p2[6] 24 io i, m p0[0] analog column mux input. 25 io i, m p0[2] analog column mux input. 26 io i, m p0[4] analog column mux input 27 io i, m p0[6] analog column mux input. 28 power vdd supply voltage. legend a: analog, i: input, o = output, and m = analog mux input. * these are the issp pins, which are not high z at por (power on reset). see the psoc mixed-signal array technical reference ma nual for details. [+] feedback
cy8c21634, cy8c21534 CY8C21434, cy8c21334, cy8c21234 document number: 38-12025 rev. *m page 11 of 43 32-pin part pinout a, i, m, p0[1] m, p2[7] m, p2[5] m, p2[3] m, p2[1] smp qfn (top view) 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 vss p0[3], a, i, m p0[7], a, i, m vdd p0[6], a, i, m p0[4], a, i, m p0[2], a, i, m vss m, 12c scl, p1[7] p0[0], a, i, m p2[6], m p3[0], m xres m, 12c sda, p1[5] m, p1[3] m, 12c scl, p1[1] vss m, 12c sda, p1[0] m, p1[2] m, extclk, p1[4] m, p1[6] p2[4], m p2[2], m p2[0], m p3[2], m p0[5], a, i, m figure 8. CY8C21434 32-pin psoc device figure 9. cy8c21634 32-pin psoc device a, i, m, p0[1] m, p2[7] m, p2[5] m, p2[3] m, p2[1] m, p3[3] qfn (top view) 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 vss p0[3], a, i, m p0[7], a, i, m vdd p0[6], a, i, m p0[4], a, i, m p0[2], a, i, m m, p3[1] m, 12c scl, p1[7] p0[0], a, i, m p2[6], m p3[0], m xres m, 12c sda, p1[5] m, p1[3] m, 12c scl, p1[1] vss m, 12c sda, p1[0] m, p1[2] m, extclk, p1[4] m, p1[6] p2[4], m p2[2], m p2[0], m p3[2], m p0[5], a, i, m figure 10. CY8C21434 32-pin sawn psoc device figure 11. cy8c21634 32-pin sawn psoc device [+] feedback
cy8c21634, cy8c21534 CY8C21434, cy8c21334, cy8c21234 document number: 38-12025 rev. *m page 12 of 43 table 6. pin definitions - cy 8c21434/cy8c21634 32-pin (qfn**) pin no. type name description digital analog 1 io i, m p0[1] analog column mux input, integrating input. 2 io m p2[7] 3 io m p2[5] 4 io m p2[3] 5 io m p2[1] 6 io m p3[3] in CY8C21434 part. 6 power smp switch mode pump (smp) connectio n to required external components in cy8c21634 part. 7 io m p3[1] in CY8C21434 part. 7 power vss ground connection in cy8c21634 part. 8 io m p1[7] i2c serial clock (scl). 9 io m p1[5] i2c serial data (sda). 10 io m p1[3] 11 io m p1[1] i2c serial clock (scl), issp-sclk*. 12 power vss ground connection. 13 io m p1[0] i2c serial data (sda), issp-sdata*. 14 io m p1[2] 15 io m p1[4] optional external clock input (extclk). 16 io m p1[6] 17 input xres active high external reset with internal pull down. 18 io m p3[0] 19 io m p3[2] 20 io m p2[0] 21 io m p2[2] 22 io m p2[4] 23 io m p2[6] 24 io i, m p0[0] analog column mux input. 25 io i, m p0[2] analog column mux input. 26 io i, m p0[4] analog column mux input. 27 io i, m p0[6] analog column mux input. 28 power vdd supply voltage. 29 io i, m p0[7] analog column mux input. 30 io i, m p0[5] analog column mux input. 31 io i, m p0[3] analog column mux input, integrating input. 32 power vss ground connection. legend a = analog, i = input, o = output, and m = analog mux input. * these are the issp pins, which are not high z at por (power on reset). see the psoc mixed-signal array technical reference ma nual for details. ** the center pad on the qfn package must be connected to ground (vss) for best mechan ical, thermal, and electrical performance . if not connected to ground, it must be electrically floated and not c onnected to any other signal. [+] feedback
cy8c21634, cy8c21534 CY8C21434, cy8c21334, cy8c21234 document number: 38-12025 rev. *m page 13 of 43 56-pin part pinout the 56-pin ssop part is for the cy8c21001 on-chip debug (ocd) psoc device. note this part is only used for in-circuit debugging. it is not available for production. figure 12. cy8c21001 56-pin psoc device table 7. pin definition s - cy8c21001 56-pin (ssop) pin no. type pin name description digital analog 1 power vss ground connection. 2 io i p0[7] analog column mux input. 3 io i p0[5] analog column mux input and column output. 4 io i p0[3] analog column mux input and column output. 5 io i p0[1] analog column mux input. 6 io p2[7] 7 io p2[5] 8 io i p2[3] direct switched capacitor block input. 9 io i p2[1] direct switched capacitor block input. 10 nc no connection. 11 nc no connection. 12 nc no connection. 13 nc no connection. 14 ocd ocde ocd even data io. 15 ocd ocdo ocd odd data output. 16 power smp switch mode pump (smp) connection to required external components. 17 power vss ground connection. 18 power vss ground connection. 19 io p3[3] ssop 1 56 vdd 2 ai, p0[7] 55 p0[6], ai 3 ai, p0[5] 54 p0[4], ai 4 ai, p0[3] 53 p0[2], ai 5 ai, p0[1] 52 p0[0], ai 6 p2[7] 51 p2[6] 7 p2[5] 50 p2[4] 8 p2[3] 49 p2[2] 9 p2[1] 48 p2[0] 10 nc 47 nc 11 nc 46 nc 12 nc 45 p3[2] 13 nc 44 p3[0] 14 ocde 43 cclk 15 ocdo 42 hclk 16 smp 41 xres 17 vss 40 nc 18 vss 39 nc 19 p3[3] 38 nc 20 p3[1] 37 nc 21 nc 36 nc 22 nc 35 nc 23 i2c scl, p1[7] 34 p1[6] 24 i2c sda, p1[5] 33 p1[4], extclk 25 nc 32 p1[2] 26 p1[3] 31 p1[0], i2c sda, sdata 27 sclk, i2c scl, p1[1] 30 nc 28 vss 29 nc vss [+] feedback
cy8c21634, cy8c21534 CY8C21434, cy8c21334, cy8c21234 document number: 38-12025 rev. *m page 14 of 43 20 io p3[1] 21 nc no connection. 22 nc no connection. 23 io p1[7] i2c serial clock (scl). 24 io p1[5] i2c serial data (sda). 25 nc no connection. 26 io p1[3] i fmtest . 27 io p1[1] crystal input (xtalin), i2c serial clock (scl), issp-sclk*. 28 power vss ground connection. 29 nc no connection. 30 nc no connection. 31 io p1[0] crystal output (xtalout), i2c serial data (sda), issp-sdata*. 32 io p1[2] v fmtest . 33 io p1[4] optional external clock input (extclk). 34 io p1[6] 35 nc no connection. 36 nc no connection. 37 nc no connection. 38 nc no connection. 39 nc no connection. 40 nc no connection. 41 input xres active high external reset with internal pull down. 42 ocd hclk ocd high-speed clock output. 43 ocd cclk ocd cpu clock output. 44 io p3[0] 45 io p3[2] 46 nc no connection. 47 nc no connection. 48 io i p2[0] 49 io i p2[2] 50 io p2[4] 51 io p2[6] 52 io i p0[0] analog column mux input. 53 io i p0[2] analog column mux input and column output. 54 io i p0[4] analog column mux input and column output. 55 io i p0[6] analog column mux input. 56 power vdd supply voltage. legend : a = analog, i = input, o = output, and ocd = on-chip debug. * these are the issp pins, which are not high z at por (power on reset). see the psoc mixed-signal array technical reference manual for details. table 7. pin definition s - cy8c21001 56-pin (ssop) (continued) pin no. type pin name description digital analog [+] feedback
cy8c21634, cy8c21534 CY8C21434, cy8c21334, cy8c21234 document number: 38-12025 rev. *m page 15 of 43 register reference this chapter lists the registers of the cy8c21x34 psoc device. for detailed register information, refer the psoc mixed-signal array technical reference manual . register conventions the register conventions specific to this section are listed in ta b l e 8 . register mapping tables the psoc device has a total register address space of 512 bytes. t he register space is referred to as io space and is divided i nto two banks. the xoi bit in the flag register (cpu_f) determines whic h bank the user is currently in. when the xoi bit is set the user is in bank 1. note in the following register mapping tables, blank fields are reserved and must not be accessed. table 8. register conventions convention description r read register or bit(s) w write register or bit(s) l logical register or bit(s) c clearable register or bit(s) # access is bit specific table 9. register map 0 table: user space name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access prt0dr 00 rw 40 ase10cr0 80 rw c0 prt0ie 01 rw 41 81 c1 prt0gs 02 rw 42 82 c2 prt0dm2 03 rw 43 83 c3 prt1dr 04 rw 44 ase11cr0 84 rw c4 prt1ie 05 rw 45 85 c5 prt1gs 06 rw 46 86 c6 prt1dm2 07 rw 47 87 c7 prt2dr 08 rw 48 88 c8 prt2ie 09 rw 49 89 c9 prt2gs 0a rw 4a 8a ca prt2dm2 0b rw 4b 8b cb prt3dr 0c rw 4c 8c cc prt3ie 0d rw 4d 8d cd prt3gs 0e rw 4e 8e ce prt3dm2 0f rw 4f 8f cf 10 50 90 cur_pp d0 rw 11 51 91 stk_pp d1 rw 12 52 92 d2 13 53 93 idx_pp d3 rw 14 54 94 mvr_pp d4 rw 15 55 95 mvw_pp d5 rw 16 56 96 i2c_cfg d6 rw 17 57 97 i2c_scr d7 # 18 58 98 i2c_dr d8 rw 19 59 99 i2c_mscr d9 # 1a 5a 9a int_clr0 da rw 1b 5b 9b int_clr1 db rw 1c 5c 9c dc 1d 5d 9d int_clr3 dd rw 1e 5e 9e int_msk3 de rw 1f 5f 9f df blank fields are reserved and must not be accessed. # access is bit specific. [+] feedback
cy8c21634, cy8c21534 CY8C21434, cy8c21334, cy8c21234 document number: 38-12025 rev. *m page 16 of 43 dbb00dr0 20 # amx_in 60 rw a0 int_msk0 e0 rw dbb00dr1 21 w amuxcfg 61 rw a1 int_msk1 e1 rw dbb00dr2 22 rw pwm_cr 62 rw a2 int_vc e2 rc dbb00cr0 23 # 63 a3 res_wdt e3 w dbb01dr0 24 # cmp_cr0 64 # a4 e4 dbb01dr1 25 w 65 a5 e5 dbb01dr2 26 rw cmp_cr1 66 rw a6 dec_cr0 e6 rw dbb01cr0 27 # 67 a7 dec_cr1 e7 rw dcb02dr0 28 # adc0_cr 68 # a8 e8 dcb02dr1 29 w adc1_cr 69 # a9 e9 dcb02dr2 2a rw 6a aa ea dcb02cr0 2b # 6b ab eb dcb03dr0 2c # tmp_dr0 6c rw ac ec dcb03dr1 2d w tmp_dr1 6d rw ad ed dcb03dr2 2e rw tmp_dr2 6e rw ae ee dcb03cr0 2f # tmp_dr3 6f rw af ef 30 70 rdi0ri b0 rw f0 31 71 rdi0syn b1 rw f1 32 ace00cr1 72 rw rdi0is b2 rw f2 33 ace00cr2 73 rw rdi0lt0 b3 rw f3 34 74 rdi0lt1 b4 rw f4 35 75 rdi0ro0 b5 rw f5 36 ace01cr1 76 rw rdi0ro1 b6 rw f6 37 ace01cr2 77 rw b7 cpu_f f7 rl 38 78 b8 f8 39 79 b9 f9 3a 7a ba fa 3b 7b bb fb 3c 7c bc fc 3d 7d bd dac_d fd rw 3e 7e be cpu_scr1 fe # 3f 7f bf cpu_scr0 ff # table 9. register map 0 table: user space (continued) name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access blank fields are reserved and must not be accessed. # access is bit specific. table 10. register map 1 table: configuration space name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access prt0dm0 00 rw 40 ase10cr0 80 rw c0 prt0dm1 01 rw 41 81 c1 prt0ic0 02 rw 42 82 c2 prt0ic1 03 rw 43 83 c3 prt1dm0 04 rw 44 ase11cr0 84 rw c4 prt1dm1 05 rw 45 85 c5 prt1ic0 06 rw 46 86 c6 prt1ic1 07 rw 47 87 c7 prt2dm0 08 rw 48 88 c8 prt2dm1 09 rw 49 89 c9 prt2ic0 0a rw 4a 8a ca prt2ic1 0b rw 4b 8b cb prt3dm0 0c rw 4c 8c cc prt3dm1 0d rw 4d 8d cd prt3ic0 0e rw 4e 8e ce prt3ic1 0f rw 4f 8f cf 10 50 90 gdi_o_in d0 rw 11 51 91 gdi_e_in d1 rw 12 52 92 gdi_o_ou d2 rw 13 53 93 gdi_e_ou d3 rw 14 54 94 d4 blank fields are reserved and must not be accessed. # access is bit specific. [+] feedback
cy8c21634, cy8c21534 CY8C21434, cy8c21334, cy8c21234 document number: 38-12025 rev. *m page 17 of 43 15 55 95 d5 16 56 96 d6 17 57 97 d7 18 58 98 mux_cr0 d8 rw 19 59 99 mux_cr1 d9 rw 1a 5a 9a mux_cr2 da rw 1b 5b 9b mux_cr3 db rw 1c 5c 9c dc 1d 5d 9d osc_go_en dd rw 1e 5e 9e osc_cr4 de rw 1f 5f 9f osc_cr3 df rw dbb00fn 20 rw clk_cr0 60 rw a0 osc_cr0 e0 rw dbb00in 21 rw clk_cr1 61 rw a1 osc_cr1 e1 rw dbb00ou 22 rw abf_cr0 62 rw a2 osc_cr2 e2 rw 23 amd_cr0 63 rw a3 vlt_cr e3 rw dbb01fn 24 rw cmp_go_en 64 rw a4 vlt_cmp e4 r dbb01in 25 rw 65 a5 adc0_tr e5 rw dbb01ou 26 rw amd_cr1 66 rw a6 adc1_tr e6 rw 27 alt_cr0 67 rw a7 e7 dcb02fn 28 rw 68 a8 imo_tr e8 w dcb02in 29 rw 69 a9 ilo_tr e9 w dcb02ou 2a rw 6a aa bdg_tr ea rw 2b clk_cr3 6b rw ab eco_tr eb w dcb03fn 2c rw tmp_dr0 6c rw ac ec dcb03in 2d rw tmp_dr1 6d rw ad ed dcb03ou 2e rw tmp_dr2 6e rw ae ee 2f tmp_dr3 6f rw af ef 30 70 rdi0ri b0 rw f0 31 71 rdi0syn b1 rw f1 32 ace00cr1 72 rw rdi0is b2 rw f2 33 ace00cr2 73 rw rdi0lt0 b3 rw f3 34 74 rdi0lt1 b4 rw f4 35 75 rdi0ro0 b5 rw f5 36 ace01cr1 76 rw rdi0ro1 b6 rw f6 37 ace01cr2 77 rw b7 cpu_f f7 rl 38 78 b8 f8 39 79 b9 f9 3a 7a ba fls_pr1 fa rw 3b 7b bb fb 3c 7c bc fc 3d 7d bd dac_cr fd rw 3e 7e be cpu_scr1 fe # 3f 7f bf cpu_scr0 ff # table 10. register map 1 table: configuration space (continued) name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access blank fields are reserved and must not be accessed. # access is bit specific. [+] feedback
cy8c21634, cy8c21534 CY8C21434, cy8c21334, cy8c21234 document number: 38-12025 rev. *m page 18 of 43 electrical specifications this section presents the dc and ac electrical specifications of the cy8c21x34 psoc device. for up to date electrical specifica tions, visit the web site http://www.cypress.com/psoc . specifications are valid for -40 o c t a 85 o c and t j 100 o c as specified, except where noted. refer table 25 on page 26 for the electrical specifications on t he internal main oscillator (imo) using slimo mode. ta b l e 11 lists the units of measure that are used in this section. table 11. units of measure symbol unit of measure symbol unit of measure o c degree celsius w microwatts db decibels ma milli-ampere ff femto farad ms milli-second hz hertz mv milli-volts kb 1024 bytes na nanoampere kbit 1024 bits ns nanosecond khz kilohertz nv nanovolts k kilohm w ohm mhz megahertz pa picoampere m megaohm pf picofarad a microampere pp peak-to-peak f microfarad ppm parts per million h microhenry ps picosecond s microsecond sps samples per second v microvolts s sigma: one standard deviation vrms microvolts root-mean-square v volts 5.25 4.75 3.00 93 khz 12 mhz 24 mhz cpu frequency vdd voltage 5.25 4.75 3.00 93 khz 12 mhz 24 mhz imo frequency vdd voltage 3.60 6 mhz slimo mode = 0 slimo mode=0 2.40 slimo mode=1 slimo mode=1 slimo mode=1 2.40 3 mhz v a l i d o p e r a t i n g r e g i o n slimo mode=1 slimo mode=0 figure 13. voltage versus cpu frequency figure 14. imo frequency trim options [+] feedback
cy8c21634, cy8c21534 CY8C21434, cy8c21334, cy8c21234 document number: 38-12025 rev. *m page 19 of 43 absolute maximum ratings operating temperature dc electrical characteristics dc chip-level specifications ta b l e 1 4 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, 3.0v to 3.6v and -40 c t a 85 c, or 2.4v to 3.0v and -40 c t a 85 c, respectively. typica l parameters apply to 5v, 3.3v, or 2.7v at 25 c and are for design guidance only. table 12. absolute maximum ratings symbol description min typ max units notes t stg storage temperature -55 25 +100 o c higher storage temperatures reduce data rete ntion time. recom- mended storage temperature is +25 o c 25 o c. extended duration storage temperatures above 65 o c degrade reliability. t a ambient temperature with power applied -40 ? +85 o c vdd supply voltage on vdd relative to vss -0.5 ? +6.0 v v io dc input voltage vss - 0.5 ? vdd + 0.5 v v ioz dc voltage applied to tri-state vss - 0.5 ? vdd + 0.5 v i mio maximum current into any port pin -25 ? +50 ma esd electro static discharge voltage 2000 ? ? v human body model esd. lu latch-up current ? ? 200 ma table 13. operating temperature symbol description min typ max units notes t a ambient temperature -40 ? +85 o c t j junction temperature -40 ? +100 o c the temperature rise from ambient to junction is package specific. see table 40 on page 38. the user must limit the power consumption to comply with this requirement. table 14. dc chip-level specifications symbol description min typ max units notes vdd supply voltage 2.40 ? 5.25 v see table 23 on page 24. i dd supply current, imo = 24 mhz ? 3 4 ma conditions are vdd = 5.0v, t a = 25 o c, cpu = 3 mhz, 48 mhz disabled. vc1 = 1.5 mhz, vc2 = 93.75 khz, vc3 = 0.366 khz. i dd3 supply current, imo = 6 mhz using slimo mode. ? 1.2 2 ma conditions are vdd = 3.3v, t a = 25 o c, cpu = 3 mhz, clock doubler disabled. vc1 = 375 khz, vc2 = 23.4 khz, vc3 = 0.091 khz. i dd27 supply current, imo = 6 mhz using slimo mode. ? 1.1 1.5 ma conditions are vdd = 2.55v, t a = 25 o c, cpu = 3 mhz, clock doubler disabled. vc1 = 375 khz, vc2 = 23.4 khz, vc3 = 0.091 khz. [+] feedback
cy8c21634, cy8c21534 CY8C21434, cy8c21334, cy8c21234 document number: 38-12025 rev. *m page 20 of 43 dc general purpose io specifications the following tables list the guaranteed maximum and minimum spec ifications for the voltage and temperature ranges: 4.75v to 5. 25v and -40 c t a 85 c, 3.0v to 3.6v and -40 c t a 85 c, or 2.4v to 3.0v and -40 c t a 85 c, respectively. typical parameters apply to 5v, 3.3v, and 2.7v at 25 c and are for design guidance only. i sb27 sleep (mode) current with por, lvd, sleep timer, wdt, and internal slow oscillator active. mid temperature range. ? 2.6 4. a vdd = 2.55v, 0 o c t a 40 o c. i sb sleep (mode) current with por, lvd, sleep timer, wdt, and internal slow oscillator active. ? 2.8 5 a vdd = 3.3v, -40 o c t a 85 o c. v ref reference voltage (bandgap) 1.28 1.30 1.32 v trimmed for appropriate vdd. vdd = 3.0v to 5.25v. v ref27 reference voltage (bandgap) 1.16 1.30 1.33 v trimmed for appropriate vdd. vdd = 2.4v to 3.0v. agnd analog ground v ref - 0.003 v ref v ref + 0.003 v table 14. dc chip-level specifications (continued) symbol description min typ max units notes table 15. 5v and 3.3v dc gpio specifications symbol description min typ max units notes r pu pull up resistor 4 5.6 8 k r pd pull down resistor 4 5.6 8 k v oh high output level vdd - 1.0 ? ? v ioh = 10 ma, vdd = 4.75 to 5.25v (8 total loads, 4 on even port pins (for example, p0[2], p1[4]), 4 on odd port pins (for example, p0[3], p1[5])). v ol low output level ? ? 0.75 v iol = 25 ma, vdd = 4.75 to 5.25v (8 total loads, 4 on even port pins (for example, p0[2], p1[4]), 4 on odd port pins (for example, p0[3], p1[5])). v il input low level ? ? 0.8 v vdd = 3.0 to 5.25. v ih input high level 2.1 ? v vdd = 3.0 to 5.25. v h input hysteresis ? 60 ? mv i il input leakage (absolute value) ? 1 ? na gross tested to 1 a. c in capacitive load on pins as input ? 3.5 10 pf package and pin dependent. te m p = 2 5 o c. c out capacitive load on pins as output ? 3.5 10 pf package and pin dependent. te m p = 2 5 o c. table 16. 2.7v dc gpio specifications symbol description min typ max units notes r pu pull up resistor 4 5.6 8 k r pd pull down resistor 4 5.6 8 k v oh high output level vdd - 0.4 ? ? v ioh = 2.5 ma (6.25 typ), vdd = 2.4 to 3.0v (16 ma maximum, 50 ma typ combined ioh budget). v ol low output level ? ? 0.75 v iol = 10 ma, vdd = 2.4 to 3.0v (90 ma maximum combined iol budget). v il input low level ? ? 0.75 v vdd = 2.4 to 3.0. [+] feedback
cy8c21634, cy8c21534 CY8C21434, cy8c21334, cy8c21234 document number: 38-12025 rev. *m page 21 of 43 dc operational amplifier specifications the following tables list the guaranteed maximum and minimum spec ifications for the voltage and temperature ranges: 4.75v to 5. 25v and -40 c t a 85 c, 3.0v to 3.6v and -40 c t a 85 c, or 2.4v to 3.0v and -40 c t a 85 c, respectively. typical parameters apply to 5v, 3.3v, or 2.7v at 25 c and are for design guidance only. v ih input high level 2.0 ? ? v vdd = 2.4 to 3.0. v h input hysteresis ? 90 ? mv i il input leakage (absolute value) ? 1 ? na gross tested to 1 a. c in capacitive load on pins as input ? 3.5 10 pf package and pin dependent. te m p = 2 5 o c. c out capacitive load on pins as output ? 3.5 10 pf package and pin dependent. te m p = 2 5 o c. table 16. 2.7v dc gpio specifications (continued) symbol description min typ max units notes table 17. 5v dc operatio nal amplifier specifications symbol description min typ max units notes v osoa input offset voltage (absolute value) ? 2.5 15 mv tcv osoa average input offset voltage drift ? 10 ? v/ o c i eboa a a. atypical behavior: i eboa of port 0 pin 0 is below 1 na at 25 c; 50 na over temperature. use port 0 pins 1-7 for the lowest leakage of 200 na. input leakage current (port 0 analog pins) ? 200 ? pa gross tested to 1 a. c inoa input capacitance (port 0 analog pins) ? 4.5 9.5 pf package and pin dependent. te m p = 2 5 o c. v cmoa common mode voltage range 0.0 ? vdd - 1 v g oloa open loop gain ? 80 ? db i soa amplifier supply current ? 10 30 a table 18. 3.3v dc operational amplifier specifications symbol description min typ max units notes v osoa input offset voltage (absolute value) ? 2.5 15 mv tcv osoa average input offset voltage drift ? 10 ? v/ o c i eboa a input leakage current (port 0 analog pins) ? 200 ? pa gross tested to 1 a. c inoa input capacitance (port 0 analog pins ) ? 4.5 9.5 pf package and pin dependent. te m p = 2 5 o c. v cmoa common mode voltage range 0 ? vdd - 1 v g oloa open loop gain ? 80 ? db i soa amplifier supply current ? 10 30 a a.atypical behavior: i eboa of port 0 pin 0 is below 1 na at 25c; 50 na over temper ature. use port 0 pins 1-7 for the lowest leakage of 200 na. table 19. 2.7v dc operational amplifier specifications symbol description min typ max units notes v osoa input offset voltage (absolute value) ? 2.5 15 mv tcv osoa average input offset voltage drift ? 10 ? v/ o c i eboa a input leakage current (port 0 analog pins) ? 200 ? pa gross tested to 1 a. c inoa input capacitance (port 0 analog pins ) ? 4.5 9.5 pf package and pin dependent. te m p = 2 5 o c. [+] feedback
cy8c21634, cy8c21534 CY8C21434, cy8c21334, cy8c21234 document number: 38-12025 rev. *m page 22 of 43 dc low power comparator specifications ta b l e 2 0 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, 3.0v to 3.6v and -40 c t a 85 c, or 2.4v to 3.0v and -40 c t a 85 c, respectively. typica l parameters apply to 5v at 25 c and are for design guidance only. dc switch mode pump specifications ta b l e 2 1 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, 3.0v to 3.6v and -40 c t a 85 c, or 2.4v to 3.0v and -40 c t a 85 c, respectively. typica l parameters apply to 5v, 3.3v, or 2.7v at 25 c and are for design guidance only. v cmoa common mode voltage range 0 ? vdd - 1 v g oloa open loop gain ? 80 ? db i soa amplifier supply current ? 10 30 a a. atypical behavior: i eboa of port 0 pin 0 is below 1 na at 25 c; 50 na over temperature. use port 0 pins 1-7 for the lowest leakage of 200 na. table 19. 2.7v dc operational amplifier specifications (continued) symbol description min typ max units notes table 20. dc low power comparator specifications symbol description min typ max units notes v reflpc low power comparator (lpc) reference voltage range 0.2 ? vdd - 1 v i slpc lpc supply current ? 10 40 a v oslpc lpc voltage offset ? 2.5 30 mv table 21. dc switch mode pump (smp) specifications symbol description min typ max units notes v pump5v 5v output voltage from pump 4.75 5. 0 5.25 v configuration of footnote. a average, neglecting ripple. smp trip voltage is set to 5.0v. v pump3v 3.3v output voltage from pump 3.00 3.25 3.60 v configuration of footnote. a average, neglecting ripple. smp trip voltage is set to 3.25v. v pump2v 2.6v output voltage from pump 2.45 2.55 2.80 v configuration of footnote. a average, neglecting ripple. smp trip voltage is set to 2.55v. i pump available output current v bat = 1.8v, v pump = 5.0v v bat = 1.5v, v pump = 3.25v v bat = 1.3v, v pump = 2.55v 5 8 8 ? ? ? ? ? ? ma ma ma configuration of footnote. a smp trip voltage is set to 5.0v. smp trip voltage is set to 3.25v. smp trip voltage is set to 2.55v. v bat5v input voltage range from battery 1.8 ? 5.0 v configuration of footnote. a smp trip voltage is set to 5.0v. v bat3v input voltage range from battery 1.0 ? 3.3 v configuration of footnote. a smp trip voltage is set to 3.25v. v bat2v input voltage range from battery 1.0 ? 2.8 v configuration of footnote. a smp trip voltage is set to 2.55v. v batsta rt minimum input voltage from battery to start pump 1.2 ? ? v configuration of footnote. a 0 o c t a 100. 1.25v at t a = -40 o c. v pump_ line line regulation (over vi range) ? 5 ? %v o configuration of footnote. a v o is the ?vdd value for pump trip? specified by the vm[2:0] setting in the dc por and lvd specification, table 23 on page 24. [+] feedback
cy8c21634, cy8c21534 CY8C21434, cy8c21334, cy8c21234 document number: 38-12025 rev. *m page 23 of 43 figure 15. basic switch mode pump circuit v pump_ load load regulation ? 5 ? %v o configuration of footnote. a v o is the ?vdd value for pump trip? specified by the vm[2:0] setting in the dc por and lvd specification, table 23 on page 24. v pump_ ripple output voltage ripple (depends on cap/lo ad) ? 100 ? mvpp configuration of footnote. a load is 5 ma. e 3 efficiency 35 50 ? % configuration of footnote. a load is 5 ma. smp trip voltage is set to 3.25v. e 2 efficiency 35 80 ? % for i load = 1ma, v pump = 2.55v, v bat = 1.3v, 10 uh inductor, 1 uf capacitor, and schottky diode. f pump switching frequency ? 1.3 ? mhz dc pump switching duty cycle ? 50 ? % a. l 1 = 2 mh inductor, c 1 = 10 mf capacitor, d 1 = schottky diode. see figure 15 . table 21. dc switch mode pump (smp) specifications (continued) symbol description min typ max units notes battery c1 d1 + psoc vdd vss smp v bat l 1 v pump [+] feedback
cy8c21634, cy8c21534 CY8C21434, cy8c21334, cy8c21234 document number: 38-12025 rev. *m page 24 of 43 dc analog mux bus specifications ta b l e 2 2 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, 3.0v to 3.6v and -40 c t a 85 c, or 2.4v to 3.0v and -40 c t a 85 c, respectively. typica l parameters apply to 5v, 3.3v, or 2.7v at 25 c and are for design guidance only. dc por and lvd specifications ta b l e 2 3 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, 3.0v to 3.6v and -40 c t a 85 c, or 2.4v to 3.0v and -40 c t a 85 c, respectively. typica l parameters apply to 5v, 3.3v, or 2.7v at 25 c and are for design guidance only. table 22. dc analog mux bus specifications symbol description min typ max units notes r sw switch resistance to common analog bus ? ? 400 800 w w vdd 2.7v 2.4v vdd 2.7v r vdd resistance of initialization switch to vdd ? ? 800 w table 23. dc por and lvd specifications symbol description min typ max units notes v ppor0 v ppor1 v ppor2 vdd value for ppor trip porlev[1:0] = 00b porlev[1:0] = 01b porlev[1:0] = 10b ? 2.36 2.82 4.55 2.40 2.95 4.70 v v v vdd must be greater than or equal to 2.5v during startup, reset from the xres pin, or reset from watchdog. v lvd0 v lvd1 v lvd2 v lvd3 v lvd4 v lvd5 v lvd6 v lvd7 vdd value for lvd trip vm[2:0] = 000b vm[2:0] = 001b vm[2:0] = 010b vm[2:0] = 011b vm[2:0] = 100b vm[2:0] = 101b vm[2:0] = 110b vm[2:0] = 111b 2.40 2.85 2.95 3.06 4.37 4.50 4.62 4.71 2.45 2.92 3.02 3.13 4.48 4.64 4.73 4.81 2.51 a 2.99 b 3.09 3.20 4.55 4.75 4.83 4.95 a. always greater than 50 mv above v ppor (porlev = 00) for falling supply. b. always greater than 50 mv above v ppor (porlev = 01) for falling supply. v v v v v v v v v pump0 v pump1 v pump2 v pump3 v pump4 v pump5 v pump6 v pump7 vdd value for pump trip vm[2:0] = 000b vm[2:0] = 001b vm[2:0] = 010b vm[2:0] = 011b vm[2:0] = 100b vm[2:0] = 101b vm[2:0] = 110b vm[2:0] = 111b 2.45 2.96 3.03 3.18 4.54 4.62 4.71 4.89 2.55 3.02 3.10 3.25 4.64 4.73 4.82 5.00 2.62 c 3.09 3.16 3.32 d 4.74 4.83 4.92 5.12 c. always greater than 50 mv above v lvd0 . d. always greater than 50 mv above v lvd3 . v v v v v v v v [+] feedback
cy8c21634, cy8c21534 CY8C21434, cy8c21334, cy8c21234 document number: 38-12025 rev. *m page 25 of 43 dc programming specifications ta b l e 2 4 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, 3.0v to 3.6v and -40 c t a 85 c, or 2.4v to 3.0v and -40 c t a 85 c, respectively. typica l parameters apply to 5v, 3.3v, or 2.7v at 25 c and are for design guidance only. table 24. dc programming specifications symbol description min typ max units notes vdd iwrite supply voltage for flash write operations 2.70 ? ? v i ddp supply current during programming or verify ? 5 25 ma v ilp input low voltage during programming or verify ? ? 0.8 v v ihp input high voltage during programming or verify 2.2 ? ? v i ilp input current when applying vilp to p1[0] or p1[1] during programming or verify ? ? 0.2 ma driving internal pull down resistor. i ihp input current when applying vihp to p1[0] or p1[1] during programming or verify ? ? 1.5 ma driving internal pull down resistor. v olv output low voltage during programming or verify ? ? vss + 0.75 v v ohv output high voltage during programming or verify vdd - 1.0 ? vdd v flash enpb flash endurance (per block) 50,000 ? ? ? erase/write cycles per block. flash ent flash endurance (total) a a. a maximum of 36 x 50,000 block endurance cycles is allowed. th is may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cyc les each (to limit the total number of cycles to 36x50,000 and that no single block ever sees more than 50,000 cycles). b for the full industrial range, the user must employ a temperat ure sensor user module (flashtemp) and feed the result to the te mperature argument before writing. refer to the flash apis application note an2015 at http://www.cypress.com under application notes for more information. 1,800, 000 ? ? ? erase/write cycles. flash dr flash data retention 10 ? ? years [+] feedback
cy8c21634, cy8c21534 CY8C21434, cy8c21334, cy8c21234 document number: 38-12025 rev. *m page 26 of 43 ac electrical characteristics ac chip-level specifications the following tables list the guaranteed maximum and minimum spec ifications for the voltage and temperature ranges: 4.75v to 5. 25v and -40 c t a 85 c, 3.0v to 3.6v and -40 c t a 85 c, or 2.4v to 3.0v and -40 c t a 85 c, respectively. typical parameters apply to 5v, 3.3v, or 2.7v at 25 c and are for design guidance only. table 25. 5v and 3.3v ac chip-level specifications symbol description min typ max units notes f imo24 internal main oscillator frequency for 24 mhz 23.4 24 24.6 a,b, c mhz trimmed for 5v or 3.3v operation using factory trim values. see figure 14 on page 18. slimo mode = 0. f imo6 internal main oscillator frequency for 6 mhz 5.75 6 6.35 a,b, c mhz trimmed for 5v or 3.3v operation using factory trim values. see figure 14 on page 18. slimo mode = 1. f cpu1 cpu frequency (5v nominal) 0.93 24 24.6 a,b a. 4.75v < vdd < 5.25v. b. accuracy derived from internal main os cillator with appropriate trim for vdd range. mhz 24 mhz only for slimo mode = 0. f cpu2 cpu frequency (3.3v nominal) 0.93 12 12.3 b, c c. 3.0v < vdd < 3.6v. see application note an2012 ?adjusting psoc microcontroller trims for d ual voltage-range operation? for information on trimming for operation at 3.3v. mhz f blk5 digital psoc block frequency 0 (5v nominal) 0 48 49.2 a,b, d d. see the individual user module data sheets for information on maximum frequencies for user modules. mhz refer to the ac digital block specifications. f blk33 digital psoc block frequency (3.3v nominal) 0 24 24.6 b,d mhz f 32k1 internal low speed oscillator frequency 15 32 64 khz jitter32k 32 khz rms period jitter ? 100 200 ns jitter32k 32 khz peak-to-peak period jitter ? 1400 ? t xrst external reset pulse width 10 ? ? s dc24m 24 mhz duty cycle 40 50 60 % step24m 24 mhz trim step size ? 50 ? khz fout48m 48 mhz output frequency 46.8 48.0 49.2 a,c mhz trimmed. using factory trim values. jitter24m1 24 mhz peak-to-peak period jitter (imo) ? 600 ps f max maximum frequency of signal on row input or row output. ? ? 12.3 mhz t ramp supply ramp time 0 ? ? s table 26. 2.7v ac chip-level specifications symbol description min typ max units notes f imo12 internal main oscillator frequency for 12 mhz 11.5 12 0 12.7 a,b, c mhz trimmed for 2.7v operation using factory trim values. see figure 14 on page 18. slimo mode = 1. f imo6 internal main oscillator frequency for 6 mhz 5.75 6 6.35 a,b, c mhz trimmed for 2.7v operation using factory trim values. see figure 14 on page 18. slimo mode = 1. f cpu1 cpu frequency (2.7v nominal) 0.093 3 3.15 a,b mhz 24 mhz only for slimo mode = 0. f blk27 digital psoc block frequency (2.7v nominal) 0 12 12.5 a,b, c mhz refer to the ac digital block specifications. f 32k1 internal low speed oscillator frequency 8 32 96 khz [+] feedback
cy8c21634, cy8c21534 CY8C21434, cy8c21334, cy8c21234 document number: 38-12025 rev. *m page 27 of 43 figure 16. 24 mhz period jitter (imo) timing diagram figure 17. 32 khz period jitter (ilo) timing diagram ac general purpose io specifications the following tables list the guaranteed maximum and minimum spec ifications for the voltage and temperature ranges: 4.75v to 5. 25v and -40 c t a 85 c, 3.0v to 3.6v and -40 c t a 85 c, or 2.4v to 3.0v and -40 c t a 85 c, respectively. typical parameters apply to 5v, 3.3v, or 2.7v at 25 c and are for design guidance only. jitter32k 32 khz rms period jitter ? 150 200 ns jitter32k 32 khz peak-to-peak period jitter ? 1400 ? t xrst external reset pulse width 10 ? ? s f max maximum frequency of signal on row input or row output. ? ? 12.3 mhz t ramp supply ramp time 0 ? ? s a. 2.4v < vdd < 3.0v. b. accuracy derived from internal main os cillator with appropriate trim for vdd range. c. see application note an2012 ?adjusting psoc microcontroller trims for dual voltage-range operation? for information on maximum frequency for user modules. table 26. 2.7v ac chip-level specifications (continued) symbol description min typ max units notes jitter24m1 f 24m jitter32k f 32k1 table 27. 5v and 3.3v ac gpio specifications symbol description min typ max units notes f gpio gpio operating frequency 0 ? 12 mhz normal strong mode trisef rise time, normal strong mode, cload = 50 pf 3 ? 18 ns vdd = 4.5 to 5.25v, 10% - 90% tfallf fall time, normal strong mode, cload = 50 pf 2 ? 18 ns vdd = 4.5 to 5.25v, 10% - 90% trises rise time, slow strong mode, cload = 50 pf 7 27 ? ns vdd = 3 to 5.25v, 10% - 90% tfalls fall time, slow strong mode, cload = 50 pf 7 22 ? ns vdd = 3 to 5.25v, 10% - 90% table 28. 2.7v ac gpio specifications symbol description min typ max units notes f gpio gpio operating frequency 0 ? 3 mhz normal strong mode trisef rise time, normal strong mode, cload = 50 pf 6 ? 50 ns vdd = 2.4 to 3.0v, 10% - 90% tfallf fall time, normal strong mode, cload = 50 pf 6 ? 50 ns vdd = 2.4 to 3.0v, 10% - 90% trises rise time, slow strong mode, cload = 50 pf 18 40 120 ns vdd = 2.4 to 3.0v, 10% - 90% tfalls fall time, slow strong mode, cload = 50 pf 18 40 120 ns vdd = 2.4 to 3.0v, 10% - 90% [+] feedback
cy8c21634, cy8c21534 CY8C21434, cy8c21334, cy8c21234 document number: 38-12025 rev. *m page 28 of 43 figure 18. gpio timing diagram ac operational amplifier specifications ta b l e 2 9 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, 3.0v to 3.6v and -40 c t a 85 c, or 2.4v to 3.0v and -40 c t a 85 c, respectively. typica l parameters apply to 5v, 3.3v, or 2.7v at 25 c and are for design guidance only. ac low power comparator specifications ta b l e 3 0 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, 3.0v to 3.6v and -40 c t a 85 c, or 2.4v to 3.0v and -40 c t a 85 c, respectively. typica l parameters apply to 5v at 25 c and are for design guidance only. ac analog mux bus specifications ta b l e 3 1 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, 3.0v to 3.6v and -40 c t a 85 c, or 2.4v to 3.0v and -40 c t a 85 c, respectively. typica l parameters apply to 5v, 3.3v, or 2.7v at 25 c and are for design guidance only. tfallf tfalls tris ef trises 90% 10% gpio pin output voltage table 29. ac operational amplifier specifications symbol description min typ max units notes t comp comparator mode response time, 50 mv overdrive 100 200 ns ns vdd 3.0v. 2.4v < vcc < 3.0v. table 30. ac low power comparator specifications symbol description min typ max units notes t rlpc lpc response time ? ? 50 s 50 mv overdrive comparator reference set within v reflpc . table 31. ac analog mux bus specifications symbol description min typ max units notes f sw switch rate ? ? 3.17 mhz [+] feedback
cy8c21634, cy8c21534 CY8C21434, cy8c21334, cy8c21234 document number: 38-12025 rev. *m page 29 of 43 ac digital block specifications the following tables list the guaranteed maximum and minimum spec ifications for the voltage and temperature ranges: 4.75v to 5. 25v and -40 c t a 85 c, 3.0v to 3.6v and -40 c t a 85 c, or 2.4v to 3.0v and -40 c t a 85 c, respectively. typical parameters apply to 5v, 3.3v, or 2.7v at 25 c and are for design guidance only. table 32. 5v and 3.3v ac digital block specifications function description min typ max units notes all functions maximum block clocking frequency (> 4.75v) 49.2 mhz 4.75v < vdd < 5.25v. maximum block clocking frequency (< 4.75v) 24.6 mhz 3.0v < vdd < 4.75v. timer capture pulse width 50 a a. 50 ns minimum input pulse width is based on the input synchronizers running at 12 mhz (84 ns nominal period). ? ? ns maximum frequency, no capture ? ? 49.2 mhz 4.75v < vdd < 5.25v. maximum frequency, with or without capture ? ? 24.6 mhz counter enable pulse width 50 ? ? ns maximum frequency, no enable input ? ? 49.2 mhz 4.75v < vdd < 5.25v. maximum frequency, enable input ? ? 24.6 mhz dead band kill pulse width: asynchronous restart mode 20 ? ? ns synchronous restart mode 50 ? ? ns disable mode 50 ? ? ns maximum frequency ? ? 49.2 mhz 4.75v < vdd < 5.25v. crcprs (prs mode) maximum input clock frequency ? ? 49.2 mhz 4.75v < vdd < 5.25v. crcprs (crc mode) maximum input clock frequency ? ? 24.6 mhz spim maximum input clock frequency ? ? 8.2 mhz maximum data rate at 4.1 mhz due to 2 x over clocking. spis maximum input clock frequency ? ? 4.1 mhz width of ss_ negated between transmissions 50 ? ? ns transmitter maximum input clock frequency maximum input clock frequency with vdd 4.75v, 2 stop bits ? ? ? ? 24.6 49.2 mhz mhz maximum data rate at 3.08 mhz due to 8 x over clocking. maximum data rate at 6.15 mhz due to 8 x over clocking. receiver maximum input clock frequency maximum input clock frequency with vdd 4.75v, 2 stop bits ? ? ? ? 24.6 49.2 mhz mhz maximum data rate at 3.08 mhz due to 8 x over clocking. maximum data rate at 6.15 mhz due to 8 x over clocking. [+] feedback
cy8c21634, cy8c21534 CY8C21434, cy8c21334, cy8c21234 document number: 38-12025 rev. *m page 30 of 43 ac external clock specifications the following tables list the guaranteed maximum and minimum spec ifications for the voltage and temperature ranges: 4.75v to 5. 25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v, 3.3v, or 2.7v at 25 c and are for design guidance only. table 33. 2.7v ac digital block specifications function description min typ max units notes all functions maximum block clocking frequency 12.7 mhz 2.4v < vdd < 3.0v. timer capture pulse width 100 a ? ? ns maximum frequency, with or without capture ? ? 12.7 mhz counter enable pulse width 100 ? ? ns maximum frequency, no enable input ? ? 12.7 mhz maximum frequency, enable input ? ? 12.7 mhz dead band kill pulse width: asynchronous restart mode 20 ? ? ns synchronous restart mode 100 ? ? ns disable mode 100 ? ? ns maximum frequency ? ? 12.7 mhz crcprs (prs mode) maximum input clock frequency ? ? 12.7 mhz crcprs (crc mode) maximum input clock frequency ? ? 12.7 mhz spim maximum input clock frequency ? ? 6.35 mhz maximum data rate at 3.17 mhz due to 2 x over clocking. spis maximum input clock frequency ? ? 4.1 mhz width of ss_ negated between transmissions 100 ? ? ns transmitter maximum input clock frequency ? ? 12.7 mhz maximum data rate at 1.59 mhz due to 8 x over clocking. receiver maximum input clock frequency ? ? 12.7 mhz maximum data rate at 1.59 mhz due to 8 x over clocking. a. 100 ns minimum input pulse width is based on the input synchronizers running at 12 mhz (84 ns nominal period). table 34. 5v ac external clock specifications symbol description min typ max units f oscext frequency 0.093 ?24.6 mhz ? high period 20.6 ? 5300 ns ? low period 20.6 ? ?ns ? power up imo to switch 150 ? ? s [+] feedback
cy8c21634, cy8c21534 CY8C21434, cy8c21334, cy8c21234 document number: 38-12025 rev. *m page 31 of 43 ac programming specifications ta b l e 3 7 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v, 3.3v, or 2.7v at 25 c and are for design guidance only. table 35. 3.3v ac external clock specifications symbol description min typ max units notes f oscext frequency with cpu clock divide by 1 0.093 ? 12.3 mhz maximum cpu frequency is 12 mhz at 3.3v. with the cpu clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements. f oscext frequency with cpu clock divide by 2 or greater 0.186 ? 24.6 mhz if the frequency of the external clock is greater than 12 mhz, the cpu clock divider must be set to 2 or greater. in this case, the cpu clock divider ensures that the fifty percent duty cycle requirement is met. ? high period with cpu clock divide by 1 41.7 ? 5300 ns ? low period with cpu clock divide by 1 41.7 ? ?ns ? power up imo to switch 150 ? ? s table 36. 2.7v ac external clock specifications symbol description min typ max units notes f oscext frequency with cpu clock divide by 1 0.093 ?3.08 0 mhz maximum cpu frequency is 3 mhz at 2.7v. with the cpu clock divider set to 1, the exte rnal clock must adhere to the maximum frequency and duty cycle requirements. f oscext frequency with cpu clock divide by 2 or greater 0.186 ? 6.35 mhz if the frequency of the external clock is greater than 3 mhz, the cpu clock divider must be set to 2 or greater. in this case, the cpu clock divider ensures that the fifty percent duty cycle requirement is met. ? high period with cpu clock divide by 1 160 ? 5300 ns ? low period with cpu clock divide by 1 160 ? ?ns ? power up imo to switch 150 ? ? s table 37. ac programming specifications symbol description min typ max units notes t rsclk rise time of sclk 1 ? 20 ns t fsclk fall time of sclk 1 ? 20 ns t ssclk data set up time to falling edge of sclk 40 ? ? ns t hsclk data hold time from falling edge of sclk 40 ? ? ns f sclk frequency of sclk 0 ? 8 mhz t eraseb flash erase time (block) ? 15 ? ms [+] feedback
cy8c21634, cy8c21534 CY8C21434, cy8c21334, cy8c21234 document number: 38-12025 rev. *m page 32 of 43 ac i 2 c specifications the following tables list the guaranteed maximum and minimum spec ifications for the voltage and temperature ranges: 4.75v to 5. 25v and -40 c t a 85 c, 3.0v to 3.6v and -40 c t a 85 c, or 2.4v to 3.0v and -40 c t a 85 c, respectively. typical parameters apply to 5v, 3.3v, or 2.7v at 25 c and are for design guidance only. t write flash block write time ? 30 ? ms t dsclk data out delay from falling edge of sclk ? ? 45 ns 3.6 < vdd t dsclk3 data out delay from falling edge of sclk ? ? 50 ns 3.0 vdd 3.6 t dsclk2 data out delay from falling edge of sclk ? ? 70 ns 2.4 vdd 3.0 table 37. ac programming specifications (continued) symbol description min typ max units notes table 38. ac characteristics of the i 2 c sda and scl pins for vdd 3.0v symbol description standard mode fast mode units min max min max f scli2c scl clock frequency 0 100 0 400 khz t hdstai2c hold time (repeated) start condition. after this period, the first clock pulse is generated. 4.0 ?0.6 ? s t lowi2c low period of the scl clock 4.7 ?1.3 ? s t highi2c high period of the scl clock 4.0 ?0.6 ? s t sustai2c set-up time for a repeated start condition 4.7 ?0.6 ? s t hddati2c data hold time 0 ?0 ? s t sudati2c data set-up time 250 ?100 a a. a fast-mode i2c-bus device may be used in a standar d-mode i2c-bus system, but the requirement t su;dat 250 ns must then be met. this is automatically the case if the device does not stretch the lo w period of the scl signal. if such device does stretch the low period of the scl signal, it must output the next data bit to the sda line t rmax + t su;dat = 1000 + 250 = 1250 ns (according to the standard-mode i2c-bus specification) before t he scl line is released. ?ns t sustoi2c set-up time for stop condition 4.0 ?0.6 ? s t bufi2c bus free time between a stop and start condition 4.7 ?1.3 ? s t spi2c pulse width of spikes are suppressed by the input filter. ? ? 0 50 ns table 39. 2.7v ac characteristics of the i 2 c sda and scl pins (fast mode not supported) symbol description standard mode fast mode units min max min max f scli2c scl clock frequency 0 100 ? ? khz t hdstai2c hold time (repeated) start condition. after this period, the first clock pulse is generated. 4.0 ? ? ? s t lowi2c low period of the scl clock 4.7 ? ? ? s t highi2c high period of the scl clock 4.0 ? ? ? s t sustai2c set up time for a repeated start condition 4.7 ? ? ? s t hddati2c data hold time 0 ? ? ? s [+] feedback
cy8c21634, cy8c21534 CY8C21434, cy8c21334, cy8c21234 document number: 38-12025 rev. *m page 33 of 43 figure 19. definition for timing for fast/standard mode on the i 2 c bus t sudati2c data set-up time 250 ? ? ?ns t sustoi2c set up time for stop condition 4.0 ? ? ? s t bufi2c bus free time between a stop and start condition 4.7 ?? ? s t spi2c pulse width of spikes are suppressed by the input filter. ? ???ns table 39. 2.7v ac characteristics of the i 2 c sda and scl pins (fast mode not supported) (continued) symbol description standard mode fast mode units min max min max sda scl s sr s p t bufi2c t spi2c t hdstai2c t sustoi2c t sustai2c t lowi2c t highi2c t hddati2c t hdstai2c t sudati2c [+] feedback
cy8c21634, cy8c21534 CY8C21434, cy8c21334, cy8c21234 document number: 38-12025 rev. *m page 34 of 43 packaging information this section shows the packaging specific ations for the cy8c21x34 psoc device with the thermal impedances for each package. important note emulation tools may require a larger area on the target pcb than the chip?s footprint. for a detailed description of the emulation tools? dimensions, refer to the document titled psoc emulator pod dimensions at http://www.cypress. com/design/mr10161 . packaging dimensions figure 20. 16-pin (150-mil) soic figure 21. 20-pin (210-mil) ssop pin 1 id 0~8 1 8 916 seating plane 0.230[5.842] 0.244[6.197] 0.157[3.987] 0.150[3.810] 0.386[9.804] 0.393[9.982] 0.050[1.270] bsc 0.061[1.549] 0.068[1.727] 0.004[0.102] 0.0098[0.249] 0.0138[0.350] 0.0192[0.487] 0.016[0.406] 0.035[0.889] 0.0075[0.190] 0.0098[0.249] dimensions in inches[mm] min. max. 0.016[0.406] 0.010[0.254] x 45 0.004[0.102] reference jedec ms-012 part # s16.15 standard pkg. sz16.15 lead free pkg. package weight 0.15gms 51-85068 *b 51-85077 *c [+] feedback
cy8c21634, cy8c21534 CY8C21434, cy8c21334, cy8c21234 document number: 38-12025 rev. *m page 35 of 43 figure 22. 28-pin (210-mil) ssop figure 23. 32-pin (5x5 mm 0.93 max) qfn 51-85079 *c 51-85188 *b e-pad x, y for this product is 3.53 mm, 3.53 mm (+/-0.11 mm) [+] feedback
cy8c21634, cy8c21534 CY8C21434, cy8c21334, cy8c21234 document number: 38-12025 rev. *m page 36 of 43 figure 24. 32-pin (5x5 mm 0.60 max) qfn important note for information on the preferred dimensions for mount ing qfn packages, see the following application note at http://www.amkor.com/products/notes_papers/mlfappnote.pdf . figure 25. 32-pin sawn qfn package e-pad x, y for this product is 3.53 mm, 3.53 mm (+/-0.11 mm) 001-06392 *a 2. based on ref jedec # mo-248 notes : 1. hatch area is solderable exposed pad bottom view n 2 1 seating plane top view 2x 2x 0.20 dia typ. n 2 1 side view 4.90 5.10 4.90 5.10 (0.93 max) 0.20 ref (0.05 max) pin #1 i.d. r0.20 0.230.05 3.50 0.50 pin #1 corner 3.50 -0.20 3.50 3.50 solderable exposed pad 0.45 001-30999 ** [+] feedback
cy8c21634, cy8c21534 CY8C21434, cy8c21334, cy8c21234 document number: 38-12025 rev. *m page 37 of 43 figure 26. 32-pin thin sawn qfn package figure 27. 56-pin (300-mil) ssop 4. dimensions are in millimeters [min/max] 2. based on ref jedec # mo-248 notes : part no. description 6. package code lr32d standard lq32d pb-free 1. hatch area is solderable exposed pad bottom view n 2 1 seating plane top view 2x 2x 0.20 dia typ. n 2 1 side view 4.90 5.10 4.90 5.10 (0.05 max) r0.30 3.55 0.50 pin #1 corner 5. maximum allowable burrs is 0.076mm -0.20 in all directions. 3. package weight: 0.0388g solderable exposed pad r 0.45 0.23 +/-0.05 3.5 3.5 3.55 001-42168 *a 51-85062 *c [+] feedback
cy8c21634, cy8c21534 CY8C21434, cy8c21334, cy8c21234 document number: 38-12025 rev. *m page 38 of 43 thermal impedances solder reflow peak temperature following is the minimum solder reflow peak temperature to achieve good solderability. table 40. thermal impedances per package package typical ja * typical jc 16 soic 123 o c/w 55 o c/w 20 ssop 117 o c/w 41 o c/w 28 ssop 96 o c/w 39 o c/w 32 qfn** 5x5 mm 0.60 max 27 o c/w 15 o c/w 32 qfn** 5x5 mm 0.93 max 22 o c/w 12 o c/w * t j = t a + power x ja ** to achieve the thermal impedance specified for the qfn package, the cent er thermal pad must be soldered to the pcb ground pl ane. table 41. solder reflow peak temperature package minimum peak temperature* maximum peak temperature 16 soic 240 o c 260 o c 20 ssop 240 o c 260 o c 28 ssop 240 o c 260 o c 32 qfn 240 o c 260 o c *higher temperatures may be required based on the solder melt ing point. typical temperatures for solder are 220 5 o c with sn-pb or 245 5 o c with sn-ag-cu paste. refer to the so lder manufacturer specifications. [+] feedback
cy8c21634, cy8c21534 CY8C21434, cy8c21334, cy8c21234 document number: 38-12025 rev. *m page 39 of 43 development tool selection this section presents the development tools available for all current psoc device families including the cy8c21x34 family. software psoc designer ? at the core of the psoc development software suite is psoc designer. used by thousands of psoc developers, this robust software has been facilitating psoc designs for half a decade. psoc designer is available free of charge at http://www.cypress.com under design resources >> software and drivers. psoc express ? as the newest addition to the psoc development software suite, psoc express is the first visual embedded system design tool that allows a user to create an entire psoc project and generate a schematic, bom, and data sheet without writing a single line of code. users work directly with application objects such as leds, switches, sensors, and fans. psoc express is available free of charge at http://www.cypress.com/psocexpress . psoc programmer flexible enough to be used on the bench in development, yet suitable for factory progra mming, psoc programmer works either as a standalone programming application or operates directly from psoc designer or psoc express. psoc programmer software is compat ible with both psoc ice-cube in-circuit emulator and psoc miniprog. psoc programmer is available free ofcharge at http://www.cypress.com/psocpro- grammer . cy3202-c imagecraft c compiler cy3202 is the optional upgrade to psoc designer that enables the imagecraft c compiler. it can be purchased from the cypress online store. at http://www.cypress.com , click the online store shopping cart icon at the bottom of the web page, and click psoc (programmable system-on-chip) to view a current list of available items. development kits all development kits can be purchased from the cypress online store. cy3215-dk basic development kit the cy3215-dk is for prototyping and development with psoc designer. this kit supports in-circuit emulation and the software interface allows users to run, halt, and single step the processor and view the content of specific memory locations. advance emulation features also supported through psoc designer. the kit includes: psoc designer software cd ice-cube in-circuit emulator ice flex-pod for cy8c29x66 family cat-5 adapter mini-eval programming board 110 ~ 240v power supply, euro-plug adapter imagecraft c compiler (registration required) issp cable usb 2.0 cable and blue cat-5 cable 2 cy8c29466-24pxi 28-pdip chip samples cy3210-expressdk psoc express development kit the cy3210-expressdk is for advanced prototyping and development with psoc express (may be used with ice-cube in-circuit emulator). it provides access to i 2 c buses, voltage reference, switches, upgradeabl e modules and more. the kit includes: psoc express software cd express development board 4 fan modules 2 proto modules miniprog in-system serial programmer minieval pcb evaluation board jumper wire kit usb 2.0 cable serial cable (db9) 110 ~ 240v power supply, euro-plug adapter 2 cy8c24423a-24pxi 28-pdip chip samples 2 cy8c27443-24pxi 28-pdip chip samples 2 cy8c29466-24pxi 28-pdip chip samples evaluation tools all evaluation tools can be purchased from the cypress online store. cy3210-miniprog1 the cy3210-miniprog1 kit allows a user to program psoc devices through the miniprog1 programming unit. the miniprog is a small, compact prototyping pr ogrammer that connects to the pc through a provided usb 2.0 cable. the kit includes: miniprog programming unit minieval socket programming and evaluation board 28-pin cy8c29466-24pxi pdip psoc device sample 28-pin cy8c27443-24pxi pdip psoc device sample psoc designer software cd getting started guide usb 2.0 cable [+] feedback
cy8c21634, cy8c21534 CY8C21434, cy8c21334, cy8c21234 document number: 38-12025 rev. *m page 40 of 43 cy3210-psoceval1 the cy3210-psoceval1 kit features an evaluation board and the miniprog1 programming unit. the evaluation board includes an lcd module, potentiometer, leds, and plenty of bread- boarding space to meet all of your evaluation needs. the kit includes: evaluation board with lcd module miniprog programming unit 28-pin cy8c29466-24pxi pdip psoc device sample (2) psoc designer software cd getting started guide usb 2.0 cable cy3214-psocevalusb the cy3214-psocevalusb evaluation kit features a development board for the cy8c24794-24lfxi psoc device. special features of the board include both usb and capacitive sensing development and debugging support. this evaluation board also includes an lcd module, potentiometer, leds, an enunciator and plenty of bread boarding space to meet all of your evaluation needs. the kit includes: psocevalusb board lcd module miniprog programming unit mini usb cable psoc designer and example projects cd getting started guide wire pack device programmers all device programmers can be purchased from the cypress online store. cy3216 modular programmer the cy3216 modular programmer kit features a modular programmer and the miniprog1 programming unit. the modular programmer includes three programming module cards and supports multiple cypress products. the kit includes: modular programmer base 3 programming module cards miniprog programming unit psoc designer software cd getting started guide usb 2.0 cable cy3207issp in-system serial programmer (issp) the cy3207issp is a production programmer. it includes protection circuitry and an industrial case that is more robust than the miniprog in a production-programming environment. note cy3207issp needs spec ial software and is not compatible with psoc programmer. the kit includes: cy3207 programmer unit psoc issp software cd 110 ~ 240v power supply, euro-plug adapter usb 2.0 cable accessories (emulation and programming) 3rd-party tools several tools have been specially designed by the following 3rd-party vendors to accompany psoc devices during devel- opment and production. specific details for each of these tools can be found at http://www.cypress.com under design resources >> evaluation boards. build a psoc emulator into your board for details on how to emulate your circuit before going to volume production using an on-chip debug (ocd) non-production psoc device, see application note an2323 ?debugging - build a psoc emulator into your board?. table 42. emulation and programming accessories part # pin package flex-pod kit a a. flex-pod kit includes a practice flex-pod and a practice pcb, in addition to two flex-pods. foot kit b b. foot kit includes surface mount feet that can be soldered to the target pcb. adapter cy8c21234-24s 16 soic cy3250-21x34 cy3250-16s oic-fk programming adapter converts non-dip package to dip footprint. specific details and ordering information for each of the adapters can be found at http://www.emulation.com . cy8c21334-24pvxi 20 ssop cy3250-21x34 cy3250-20ssop-fk CY8C21434-24lfxi 32 qfn cy3250- 21x34qfn cy3250-32qfn-fk cy8c21534-24pvxi 28 ssop cy3250-21x34 cy3250-28ssop-fk cy8c21634-24lfxi 32 qfn cy3250- 21x34qfn cy3250-32qfn-fk [+] feedback
cy8c21634, cy8c21534 CY8C21434, cy8c21334, cy8c21234 document number: 38-12025 rev. *m page 41 of 43 ordering information package ordering code flash (bytes) sram (bytes) switch mode pump temperature range digital blocks analog blocks digital io pins analog inputs a analog outputs xres pin 16 pin (150-mil) soic cy8c21234-24sxi 8k 512 yes -40 c to +85 c 4 4 12 12 a 0 no 16 pin (150-mil) soic (tape and reel) cy8c21234-24sxit 8k 512 yes -40 c to +85 c 4 4 12 12 a 0 no 20 pin (210-mil) ssop cy8c21334-24pvxi 8k 512 no -40 c to +85 c 4 4 16 16 a 0 yes 20 pin (210-mil) ssop (tape and reel) cy8c21334-24pvxit 8k 512 no -40 c to +85 c 4 4 16 16 a 0 yes 28 pin (210-mil) ssop cy8c21534-24pvxi 8k 512 no -40 c to +85 c 4 4 24 24 a 0 yes 28 pin (210-mil) ssop (tape and reel) cy8c21534-24pvxit 8k 512 no -40 c to +85 c 4 4 24 24 a 0 yes 32 pin (5x5 mm 0.93 max) qfn b CY8C21434-24lfxi 8k 512 no -40 c to +85 c 4 4 28 28 a 0 yes 32 pin (5x5 mm 0.93 max) qfn b (tape and reel) CY8C21434-24lfxit 8k 512 no -40 c to +85 c 4 4 28 28 a 0 yes 32 pin (5x5 mm 0.60 max) qfn b CY8C21434-24lkxi 8k 512 no -40 c to +85 c 4 4 28 28 a 0 yes 32 pin (5x5 mm 0.60 max) qfn b (tape and reel) CY8C21434-24lkxit 8k 512 no -40 c to +85 c 4 4 28 28 a 0 yes 32 pin (5x5 mm 0.93 max) qfn b cy8c21634-24lfxi 8k 512 yes -40 c to +85 c 4 4 26 26 a 0 yes 32 pin (5x5 mm 0.93 max) qfn b (tape and reel) cy8c21634-24lfxit 8k 512 yes -40 c to +85 c 4 4 26 26 a 0 yes 32 pin (5x5 mm 0.93 max) sawn qfn CY8C21434-24ltxi 8k 512 no -40 c to +85 c 4 4 28 28 a 0 yes 32 pin (5x5 mm 0.93 max) sawn qfn b (tape and reel) CY8C21434-24ltxit 8k 512 no -40 c to +85 c 4 4 28 28 a 0 yes 32 pin (5x5 mm 0.60 max) thin sawn qfn CY8C21434-24lqxi 8k 512 no -40 c to +85 c 4 4 28 28 a 0 yes 32 pin (5x5 mm 0.60 max) thin sawn qfn (tape and reel) CY8C21434-24lqxit 8k 512 no -40 c to +85 c 4 4 28 28 a 0 yes 32 pin (5x5 mm 0.93 max) sawn qfn b cy8c21634-24ltxi 8k 512 yes -40 c to +85 c 4 4 26 26 a 0 yes 32 pin (5x5 mm 0.93 max) sawn qfn b (tape and reel) cy8c21634-24ltxit 8k 512 yes -40 c to +85 c 4 4 26 26 a 0 yes 56 pin ocd ssop cy8c21001-24pvxi 8k 512 yes -40 c to +85 c 4 4 26 26 a 0 yes a. all digital io pins also c onnect to the common analog mux. b. refer to the section 32-pin part pinout on page 11 for pin differences. [+] feedback
cy8c21634, cy8c21534 CY8C21434, cy8c21334, cy8c21234 document number: 38-12025 rev. *m page 42 of 43 ordering code definitions cy 8 c 21 xxx-24xx package type: thermal rating: px = pdip pb-free c = commercial sx = soic pb-free i = industrial pvx = ssop pb-free e = extended lfx/lkx = qfn pb-free ax = tqfp pb-free speed: 24 mhz part number family code technology code: c = cmos marketing code: 8 = cypress psoc company id: cy = cypress [+] feedback
document number: 38-12025 rev. *m revised april 18, 2008 page 43 of 43 all products and company names mentioned in this document may be the trademarks of their respective holders. cy8c21634, cy8c21534 CY8C21434, cy8c21334, cy8c21234 ? cypress semiconductor corporation, 2004-2008. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. document history page document title: cy8c21234/cy8c2 1334/CY8C21434/cy8c21534/cy8c21634 psoc ? mixed-signal array document number: 38-12025 revision ecn orig. of change description of change ** 227340 hmt new silicon and document (revision **). *a 235992 sfv updated overview and electrical spec. chapters, along with revisions to the 24-pin pinout part. revised the register mapping tabl es. added a ssop 28-pin part. *b 248572 sfv changed title to include all part #s. changed 28-pin ssop from CY8C21434 to cy8c21534. changed pin 9 on the 28-pin ssop from smp pin to vss pin. added smp block to architecture diagram. update electrical specifications . added another 32-pin mlf part: cy8c21634. *c 277832 hmt verify data sheet standards from sfv memo. add analog input mux to applicable pin outs. update psoc characteristics table. update diagrams and specs. final. *d 285293 hmt update 2.7v dc gpio spec. add reflow peak temp. table. *e 301739 hmt dc chip-level specification changes. update links to new cy.com portal. *f 329104 hmt re-add pinout issp notation. fix tmp register name s. clarify adc feature. update electrical specifications. update reflow peak temp. table. add 32 mlf e-pad dimensions. add thetajc to thermal impedance table. fix 20-pin package order number. add cy logo. update cy copyright. *g 352736 hmt add new color and logo. add url to preferred dimensions for mountin g mlf packages. update transmitter and receiver ac digital block electrical specifications. *h 390152 hmt clarify mlf thermal pad connection info. replac e 16-pin 300-mil soic with correct 150-mil. *i 413404 hmt update 32-pin qfn e-pad dimensions and rev. *a. update cy branding and qfn convention. *j 430185 hmt add new 32-pin 5x5 mm 0.60 thickness qfn package and diagram, CY8C21434-24lkxi. update thermal resistance data. add 56-pin ssop on-chip debug non-production part, cy8c21001-24pvxi. update typical and recomm ended storage temperature per industrial specs. update copyright and trademarks. *k 677717 hmt add capsense snr requirement reference. add new dev. tool section. add cy8c20x34 to psoc device characteristics table. add low po wer comparator (lpc) ac/dc electrical spec. tables. update rev. of 32-lead (5x5 mm 0.60 max) qfn package diagram. *l 2147847 uvs/pyrs added 32-pin qfn sawn pin diagram, package diagram, and ordering information. *m 2273246 uvs/aesa added 32 pin thin sawn package diagram. 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